1. Technical Field
The present invention relates to thin film technology, and more particularly to controlling the melt front of thin film applications.
2. Description of the Related Art
Heterogeneous material integration has become an important enabling technology for a wide range of commercial and military applications. Examples include silicon-on-insulator (SOI) technology for complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs). Advances in wafer bonding are cornerstone to emergence of these new heterogeneous substrates; it allows one type of material to be combined with another type of material for which growth or deposition options do not exist.
There are currently a limited number of wafer-scale bonding methods. One such method is semiconductor wafer bonding which relies on atomic-scale bonding of flat, mirror-polished glass or semiconductor surfaces. Many of the other bonding techniques such as anodic, thermocompression, epoxy, eutectic or solder-based bonding are most often performed at the chip, package or die level. It is, in general, difficult to achieve large area void-free bonding using methods that employ a bonding agent (intervening materials such as metallics or polymers). Moreover, large-area bonding of thin, strained, brittle films with potentially high curvature onto arbitrary rigid substrates is non-existent.
Efforts to (i) create thin-film substrates from bulk materials (i.e., semiconductors) and (ii) form thin-film device layers by removing device layers from the underlying bulk substrates on which they were formed are ongoing. For example, epoxy has been used to bond a III-V based solar cell structure to a silicon handle wafer. However, the epoxy method does not allow higher temperature excursions without degradation of bonding material. In addition, filled epoxies limit the thermal conductivity for some applications. Moreover, conventional wafer bonding is usually performed between two rigid wafers, and all available tooling is specifically designed for this situation. One of the major problems associated with bonding thin, curved, and potentially rough layers is that there is a larger density of trapped air or voids at the interface compared to bonding rigid, polished wafers.